1. Technical Field
The present invention provides an apparatus and method for incorporating driver sizing into buffer insertion. Specifically, the present invention provides an apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique.
2. Description of Related Art
It is now widely accepted that interconnect performance is becoming increasingly dominant over transistor and logic performance in the deep submicron regime. Buffer insertion is now a fundamental technology used in modern VLSI design methodologies. As gate delays decrease with increasing chip dimensions, however, the number of buffers required quickly rises. It is expected that close to 800,000 buffers will be required for 50 nanometer technologies. It is critical to automate the entire interconnect optimization process to efficiently achieve timing closure.
The problem of inserting buffers to reduce the delay on signal nets has been recognized and studied. A closed form solution for two-pin nets has been proposed by van Ginneken. Van Ginneken's dynamic programming algorithm, described in “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” Int'l Symposium on Circuits and Systems, 1990, pp. 865-868, which is hereby incorporated by reference, has become a classic in the field. Given a fixed Steiner tree topology, the van Ginneken algorithm finds the optimal buffer placement on the topology under an Elmore delay model for a single buffer type and simple gate delay model. Several extensions to this work have been proposed. Together, these enhancements make the van Ginneken style of buffer insertion quite potent as it can handle many constraints, buffer types, and delay models, while retaining optimality under many of these conditions. Most recently, research on buffer insertion has focused on accommodating various types of blockage constraints.
In addition to buffer insertion, driver sizing is an effective transform for achieving timing closure in placed designs. Driver sizing involves trying different size driver circuit elements for a net and determining an optimum result for the net. With driver sizing, drivers are instantiated at various power levels, among other characteristics, while preserving the same logic function. Choosing a different driver size will result in different timing and power characteristics for the design. The goal is to pick the driver size which results in the best possible timing for the given net.
Typically, buffer insertion and driver sizing are performed individually, sequentially, and perhaps even iteratively alternating between the two optimization techniques. The problem is that the two optimization techniques of buffer insertion and driver sizing affect each other. Thus, optimizing a net using these optimization techniques in sequence can yield a solution that is sub-optimal.
Thus, it would be beneficial to have an apparatus and method for incorporating driver sizing into buffer insertion such that driver sizing and buffer insertion are performed simultaneously.